1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a semiconductor memory system and an operating method thereof including a plurality of memory devices of multi-plane array.
2. Description of the Related Art
In general, semiconductor memory devices are classified into volatile memory devices, such as a dynamic random access memory (DRAM) and a static random access memory (SRAM), and nonvolatile memory devices, such as a programmable read only memory (PROM), an erasable PROM (EPROM), an electrically EPROM (EEPROM), and a flash memory device. The distinguishable characteristic between the volatile memory device and the nonvolatile memory device from each other is whether or not data stored in a memory cell is retained.
Whether data is retained or not may be dependent on a memory cell structure. That is, a volatile memory device and a nonvolatile memory device have different memory cell structures. From a viewpoint of the memory cell structure, data stored in a volatile memory device is not retained after a certain time, whereas data stored in a nonvolatile memory device is retained even after a certain time. Accordingly, in the case of a volatile memory device, a refresh operation must be performed in order to retain data. In contrast, in the case of a nonvolatile memory device, a refresh operation is not essential, which is suitable for a recent tendency toward lower power and high degree of integration and makes nonvolatile memory devices widely used as storage media for portable devices.
Recently, package technology for semiconductor memory devices is developing in order to meet user's needs. A multi-chip packaging is recently being proposed as package technology for semiconductor memory devices. The multi-chip packaging refers to the formation of a plurality of semiconductor devices into a single chip, wherein homogeneous semiconductor devices are stacked to increase the memory capacity or heterogeneous semiconductor devices of different functions are stacked to improve desired performance.
A semiconductor memory system capable of controlling semiconductor memory devices more efficiently is proposed below.